Pulse resolution circuit with gated delay means and flip-flop providing selective separation between random inputs



C. E. KRAUSE Nov. 26, 1963 S N m M mE S E .WW D TP CN D mm1 @sm Hmm TIM I D W IN V Hom U um W C R P E I 0 Cn-IPHN N mv.. O P T I I TLM WFA ODP www R E w U D..

5 Sheets-Sheet 1 Filed Aug. 15, 1962 Smfw Nov. 26, 1963 c. E. KRAusE 3,112,450

PULSE RESOLUTION CIRCUIT WITH GATED DELAY MEANS AND FLIP-ELOI PROVIDING sELEcTIvE SEPARATION BETWEEN RANDOM INPUTs Filed Aug. l5, 1962 5 Sheets-Sheet 2 F/G. 2 D /IVIDUT PULSE /Q/Q/l/[S O/V TERM/NAL 20 AFTER Ta /6 Y l /A/Pus t2+02 O 1 GATE 32 /8 /A/Purs t+03 7 0 GATE 34 /A/VE/vop C. E KRAUSE @y A (To/:wey

Nov. 26, 1963 c. E. KRAusE 3,112,450

PULSE RESOLUTION CIRCUIT WITH GATED DELAY MEANS AND FLIP-FLOP PROVIDING SELECTIVE SEPARATION BETWEEN RANDOM INPUTS Filed Aug. l5, 1962 5 Sheets-Sheet 5 /A/PUT PULSE ARR/VES 0^/ TERM/NAL 20 BEFORE 75 /0` Y t] l I 1/ Y /6- -uvm/r @+02 /a- /A/PUK +03 ro 2 @T534 ,4* t/-l-D/ /m/E/v To@ ATTORNEY c.; mm1/5E Nov. `26, 1963 AUsE 3,112,450

MEANS C. E. KR PULSE RESOLUTION CIRCUIT WITH GATED. DELAY AND FLIP-FLOP PROVIDING SELECTIVE SEPARATION BETWEEN RANDOM INPUTS Filed Aug. 15, 1962 5 Sheets-Sheet 4 /VPU T PULSE ARP/VES O/V TE/QM//VAL20 DUR/NG l0- t/ f /A/purs /6 @+02 ro GATE 32 I /8- t /A/Purs 2 +03 To GATE34 3A- A l g-I-Dg /A/L/EA/op By C. E. KRAUSE ATTORNEY Nov. 26, 1963 c. E. KRAUsE 3,112,450

PULSE RESOLUTION CIRCUIT WITH GATED DELAY MEANS AND ELIP-ELQP PROVIDING sELEcIIvE SEPARATION BETWEEN RANDOM INPUIs Filed Aug. l5, 1962 5 Sheets-Sheet 5 PULSE-s ARR/Vf s/MULTA A/[OU'SLV /6 /A/zO/rs f2 D2 GATE-s I /a /A/Purs t? +03 SI1-MGM@ A 7' TOPNEV United States Patent O PULSE RESLUT* tiRCUlT WHTH GATED DELAY MEANS AND FlL-FLOP PRVIDHNG SELECTWE EPARA'HON BEEK/EEN RNB'M INPUTS Charles E. Krause, Columbus, (Ehio, assigner to Beil Telephone Laboratories, incorporated, New York, NSY., a corporation of New Yori:

Filed Aug. 15, 1962, Ser. No. 2117,@96 l2 Claims. (Cl. 323-469) This invention relates to pulse circuits and, more particularly, to a circuit for providing suiiicient resolution time between randomly occurring pulses.

Electronic designers have been increasingly concerned with the ability of components to operate reliably in the short time intervals which are now required in many electronic circuits. Such circuits must be able to respond to pulses of quite narrow duration and spacing, often in the microsecond range. Consequently, the problem is presented of providing suiiicient time between such signals to allow a high speed circuit to properly operate in response thereto.

These high speed requirements are evident in many modern communications systems. With the advent of the electronic switching systems in the telephone industry, and the fully electronic central oliice, telephone circuits now join with the other switching arrangements needing such high speed operation. For example, a magnetic core memory may comprise an essential part of a test set for an electronic control oiiice and since an occasion may arise when two pulses are transmitted to the memory within very short intervals of each other, provision must be made to distinguish between such signals when the system is being tested. Similarly, in computer technology or in many other counting arrangements, input signals will be delivered to the digital machine or counter from two or more sources of randomly occurring pulses. Should these pulses be separated by a time interval greater than the machines resolution time, the circuit will have no trouble in operating. The problem arises, however, when these signals occur closer together, the worst case condition being when the two or more signals occur simultaneously. In such a situation, were it not for the provision of a structure such as the instant invention, the circuit presumably responsive to these input signals might completely ignore one or more of them. This would obviously destroy a count or an instruction to a memory address, or hamper any one of a number of similar functions.

in the past, this problem has been partially overcome in certain arrangements by merely arbitrarily delaying one of, say, two inputs by a fixed amount; assuming that the two inputs are completely random, this system is as ineiTective as one which provides no delay at all. This can be seen from the fact that should a pulse arrive at the second input after a lapse of time equal to the iixed amount by which the rst pulse is delayed, a case of simultaneous pulsing at the circuits output terminals is once again encountered.

Furthermore, some prior art devices were ineective due to their inability to respond properly when either one or more of the input signals arrived at the circuit and encountered a transient condition in the receiving crcuit. With the increasing prevalence of switching circuits, such transient conditions have often been troublesome in their frequency of occurrence, but an efcent pulse resolution circuit, for example, must be able to deal as eiiectively with transients as with stable electrical levels.

It is an object of this invention to provide an improved pulse resolution circuit.

It is a further object of this invention to provide a pulse resolution circuit which is more flexible in design H and which is capable of determining which one of a plurality of delay units to activate.

it is also an object of this invention to furnish a pulse separator circuit which is capable of providing suiiicient resolution time between randomly occurring pulses on different inputs to the same circuit. y Another object of this invention is to provide a pulse circuit which will perform reliably even as to input signals encountering transient conditions in the pulse separator circuitry.

In one illustrative embodiment of this invention, a pulse resolution circuit with two input terminals is disclosed. A pulse arriving at the iirst of these inputs is always effective to energize a first delay unit and is thereby delayed by the time value of the unit. A pulse arriving at the second input to the circuit may be transmitted to the corresponding second output through one of two delay units, one of these units providing a longer delay and one a shorter delay than that provided by the delay unit associated with the iirst input terminal.

Should two input pulses arrive at the respective input terminals spaced by an amount greater than a predetermined interval (such interval being electrically represented by the duration of the output signal from a gate generator triggered by the arrival of the first pulse), both pulses will proceed through the circuit in normal fashion, the first pulse being delay by its associated delay unit and the second pulse bieng delay by the shorter of the two delay units associated with the second input. The shorter delay unit is selected in such a situation by circuitry whose combined operation has the effect of blocking an output gate which is associated with the longer of the two delay units, and therefore the only available transmission channel for the second input pulse is through the shorter delay unit. Thus, if pulses arrive at the two input terminals more than, say, 50 microseconds apart, the first pulse could be delayed by 25 microseconds, while the second pulse would be delayed by the shorter of its two associated delay units, say 3 microseconds, instead of the longer delay of perhaps 47 microseconds.

lf the second input pulse to the circuit arrives within the predetermined interval after the arrival of the first pulse, the circuit must operate so as to provide suiiicient resolution time for the device to which these pulses will be delivered. Operating similarly as above, the iirst pulse will be delayed by its uniformly associated delay, while the second pulse is delayed by the longer of the two delay units coupled to the second input terminal. The outputs associated with the iirst and second input terminals thus exhibit pulse signals sufficiently far apart in time so that the device to receive these signals may properly operate. For example, the pulses might arrive within a predetermined interval of 50 microseconds of each other, and while the iirst pulse would again be delayed by the fixed 25 microsecond delay mentioned supra, the second pulse would now be delayed by the longer of its two possible delay periods, e.g., 47 microseconds instead of 3 microseconds.

A situ-ation which can be classified as the most critical, although from a probability standpoint the one which is the least frequent, is that in which pulses arrive simultaneously at the tirs-t and the second input terminals to the circuit. The instant invention is particularly adapted to cope with such an occurrence. As is the case with any sequence of arriving pulses, the pulse arriving at the iirst input terminal energizes its associated delay unit and gate generator. The pulse arriving at the second input terminal can be, it will be recalled, delayed by one of two differently timed intervals. The output of the gate generator, which acts as the input signal to other circuitry controlling a bistable device, may be in a transient condition during the time when the second input pulse is also transmitted to this circuitry. It would initially appear that a problem might exist if ambiguous signals were provided to the inputs o the histahle device (hip-flop). T his might result, under extreme circumstances, in simultaneous pulsing of both the set and reset inputs to the dip-flop, normally an intolerable condition due to the uncertainty associated with the llip-lops out-put in such a situ-ation.

lt is recognized that the flip-liep, when both of its inputs are pulsed simultaneously, will give only a l -or a O output, but the one of these two outputs chosen is usually critical to the circuits operation. However, the instant invention is so arranged that in the case of simultaneous arrival o pulses at the two inputs to the circuit, the resolution time maintained between the two output signals will be the same irrespective of which of the two delay units associated with the second input terminal is energized. This result is obtained by making the diie-rence between the longer of the two delay units associated with the second input terminal and the delay unit associated with the lirst input terminal equal in time separation to the difference between the delay' represented by the first delay unit and that represented by the shorter of the delay units associated with the second input terminal.

Thus, illustratively, when two pulses arrive at the circuits two inputs simultaneously, the pulse arriving at a rst of the inputs is delayed by its associated 25 microsecond delay. Assuming that some uncertainty may be associated with the operation of the ilip-llop, the pnl-se at the second input might be delayed by either of the two illustrative delay values, ie., 3 microseconds or 47 microseconds. But it is immediately apparent that whichever of the two delays is in fact operative to delay the pulse at the second input, the output resolution time will be the samenamely 2.2 microseconds furnished by (Z5-3) microseconds if the circuit should select the 3 mlcrosecond delay .'for the pulse at the second input, or by (47-25) microseconds if the circuit should select the 47 microsecond delay for the pulse at the second input.

A feature of this invention includes facilities for uniformly separating randomly occurring pulses at two separate input terminals by at least a minimum predetermined interval.

A further feature of this invention includes flexible delaying means whereby a pulse arriving at one input terminal is delayed by a first interval and a pulse arriving at the second input terminal is delayed by one of two different time intervals depending on the time proximity of the pulses at the two inputs.

Ano-ther feature of this invention includes a bistable device for determining which of the two delay elements associated with the second input terminal is effective in elaying a pulse at that input.

An additional feature of this invention includes means for properly responding to lthe simultaneous arrival of pulses at the circuit inputs when a transient condition is encountered.

These and other objects and features of this invention will become apparent when taken in conjunction with the following specication, the appended claims and the drawing in which:

FlG. l is a schematic representation of an illustrati-ve pulse resolution circuit embodying the principles of this invention', and

FlGS. 2, 3, 4 .and 5 are time diagrams respectively illustrating symbolic electrica-l conditions at various points in the circuit of FIG. l in the cases or" pulses arriving at the circuits inputs: (cz) suliiciently widely spaced, (b) randomly spaced in a different sequence trom FlG. 2, (c) within a predetermined interval of cach other, or (d) simultaneously; the base lines lin each of FlGS. 2, 3, 4 and 5 represent the lower of two circuit voltage levels,

2l the upper of these two levels being similarly shown therein and representing the cirouits steady-state conditionthese levels may be, as discussed infra, 0 volt and +45 volts respectively.

The pulse resolution circuit illustrated in FG. l includes two input terminals lil and Ztl and two output conductors ld and 37 providing the separated pulse signals to a utilization circuit 33. Coupled to terminal il) are gate generator ll and delay unit 13; delay units l5 and 17 are associated with terminal 2i?. The delay units i3, l5 and 17 as well as the gate generator ll are similarly constituted and may advantageously comprise monostahle multivibrators such as that shown on page 6G() of Pulse and Digital Circuits by Millman and Taub (McGraw- Hill Book Company, Inc., l956). The gate generator ll is triggered hy a pulse at terminal ll and provides the standard monostable multivibrator level output shown at conductor l2 in FIG. 1. The output signal of the generator il remains inthe higher of two possible states during Tb -unti'l it is triggered by a signal at terminal lli. After such .a triggering signal arrives, the output signal at conductor l2 falls to the lower of the two conditions, this being the quasi-stable condition of the multivibrator existing for the time interval denoted as Ta. ln switching from the higher stable state to the quasi-stable state, and also in switching back from the quasi-stable state to the stable state, two transient conditions denoted respectively as T1 and T2 are indicated. 'Phe pulse outputs from elements 13, 15 and i7 may be obtained by differentiating and rectifying the output signal of a monostable multivibrator in a well-known manner.

The AND gates i9 and Z5 are responsive to simultaneously applied signals of the lower of the two circuit levels (illustrativelyg these levels may be 4.5 volts and O volt, and these values will hereinafter be referred to where appropriate) at their respective input terminals 21 and 22 and 26 and 27. That is, AND gate 19' will deliver a pulse output signal on its `lead 23 if both of the signals on leads 2l and 22 are simultaneously at the circu-its lower voltage level, le., 0 volt; similarly AND gate 25 will deliver a pul-se output signal on its lead 2d if both of the signals on its input leads 26 and 27 are simultaneously at the lower of the two circuit voltage levels. Inverter Z4 serves to invert the gating signal ex-v isting on lead 12 shown in FlG. l, the inverted signal being transmitted to lead 26. The dip-flop 29 iS IeSPOLU' sive to pulses from leads 23- and 2S transmitted to lits set and reset terminals, S and R respectively. Asitlmmg that the two voltage levels used in the circuit are H5 volts and O volt, the l output of the flip-liep 29 on lead 3d will normally be at 0 volt, while the 0 output on lead 3i will normally be at 4.5 volts. When the set input S is pulsed by a 4.5 to 0 volt pulse from lead Z3, 'he iiip-iiops outputs will' respond thereto with the l output on lead 36 switching to 4.5 volts, and the 0" output on lead 31 dropping to 0 volt. Such a condition will he maintained until a reset pulse is provided from lead 2S to the -llip-liop, in which case the llip-liops two output terminals will return to their original conditions. If a subsequent reset pulse should now arrive from lead 28 while lead 31 is at 4.5 volts, the iiip-ops output terminals would remain unaffected.

rvihe AND gates 52 and 3dare identical to the gates l@ and 2S described supra, gate E?. being responsive toy the simultaneous lower voltage level signals on leads lo'v and 3l, and gate being responsive to similarly arrangedv signals on `leads ld and Appropriate pulsing of the cir-cuit will result in the transmission of a pulse from either AND gate 32 or AND gate 34 on leads 33 or 35 respectively, to OR gate 36, the latter being responsive to pulses of the lower of the two voltage levels in the circuit on either lead 33 or 35 to prctvide an output pulse on lead '37 to the utilization circuit 3S. K

Case I: Input Pulse Arrives on Terminal 20 After T a rTaking the pulse resolution circuit of FiG. l in conjunction with the timing diagram of FlG. 2, We see the situation in which pulses arrive at the respective input terminals it? and 2t? such that the input on terminal Ztl occurs during time Tb and after time Ta, the latter being the nominal decision interval of the circuit. The resolution time .of utilization circuit 33 is represented electrically by the minimum time separation that the instant invention can provide under the worst case condition of the simultaneous arrival of pulses, to be discussed infra in Case lV. Following 4the timing sequence shown in 1C. 2, and with the voltage levels at the correspondingly numbered terminals or conductors of FIG. l represented on the common vertical axis shown in FIG. 2, it is seen that an input pulse arrives at terminal lil at time t1. Such a pulse initially activates gate generator lil producing the quasi-stable lower vol-tage condition mentioned supra with regard to conductor l2, and also shown in FlG. 2. A second input pulse is now assumed to arrive at terminal 29 at time t2 after the output signal on conductor lf2 has returned to its monostable upper voltage level, this input time sequence being shown in the rst three lines of FlG. 2.

The pulse input signal at terminal 2l?l cari be delayed either by the time interval provided by delay unit l5 or by delay unit l?, the respective delays being denoted as D2 and D3. it has been postulated that the pulse at terminal 2d only arrives there during Tb, this time representing the interval during which the output of gate generator il is at its stable upper voltage level of 4.5 volts as shown in the time sketch at conductor l2 in FIG. l. Therefore, when the input pulse arrives at terminal Ztl and is thereafter delivered on conductors 22 and 27 to AND gates t9 and Z5 respectively, the signals at the other inputs to these two AND gates, namely conductors El and 25 respectively, will be as follows: conductor 2l will exhibit 4.5 volts since "i", has already elapsed, while conductor 2e will exhibit the inverted signal thereby providing a volt level to AND gate 25.

By this analysis, it is seen that when the pulse signal arrives at terminal 21? with the time sequence of Case l applied, AND gate 25 will be enabled and will deliver a negative-going pulse on lead 21S to the reset terminal R of the flip-hop 29. Since the flip-hop 29 is assumed to have been in .a reset state prior to this sequence of pulses, such an input signal to its reset terminal R will have no eiiect on the signals existing at the Jdip-floris output conductors 3% and rl`hereore, as mentioned supra with respect to the operation of flip-flop 2?, a 0 volt level is maintained on conductor Si?, while a 4.5 volt level is maintained on conductor 3l; these Voltage levels ar indicated at the correspondingly numbered lines in FlG. 2.

rl"ne arrival of the pulse at terminal 'Ztl at time t2 as shown in FIG. 2 also has the effect of `activating the pulse output delay elements l' and l?. Such a pulse output is provided .at the respective output terminals le and ld of these two delay elements at the times trl-D2 and fyi-D3 respectively. The inputs to AND gate 32, being the voltage signals on leads lo and 3l, are seen in 2 to never be simultaneously at the same requisite lower voltage level that will enable the gate. The inputs to AND gate 3e?, on the other hand, are the uniform O volt level ou lead 3d and the G volt pulse at time t2|'-D3 as shown in FIG. 2; the presence oi two simultaneous 0 volt signals at the inputs to AND gate 34S enable that gate and provide a similar pulse output on conducto-r '35 at time ffl-D3. Conductor 33 however, since AND gate 32. remains disabled, exhibits a constant 4.5 volt level.

The OR gate 36 passes the lower level pulses to output conductor 37' when such a pulse arrives either on lead 33 or on lead 3S, so that a pulse output will be delivered on Ilead 37 to the utilization circuit 31S at time tz-l-Dg as shown in the bottom line of `FlG. 2. rThe prior arrival of a pulse at terminal l0' had the eil-ect of also energizing delay unit i3, thereby providing a pulse output on lead l@ to utilization circuit 38 at time trl-D1 as shown in the next to the bottom line of FIG. 2. Thus, it can be seen that the path selected by tlip-tlop 2@ for the transmission of the pulse arriving at input terminal during time Tb and lafter time T2, to utilization circuit 38, is the path which includes terminal 2li, delay unit i7, conductor 13, AND gate 34, conductor Se', Ol?` gate 3o and conductor 37.

The structure of the circuit is such that the delay D3 provided by unit 17 is substantially shorter in time than is the delay D2 provided by unit l5; `and since the operation of the output signal of the gate generator Ell has indicated 4to the llip-ilop 29 by means of the AND gates t9 and 25 that the pulse has arrived at terminal 2lil sufciently far removed in time from the pulse at terminal itl, the ip-lop 29 should disable AND gate 312 associated with the longer delay D2 provided by delay unit l5, and also enable AND gate associated with the much sho-rter delay D3 provided by delay unit l? (delay D3 may be il'lustfratively chosen to be just greater than the operate time of the ilip-tlop 29). This is precisely the Way in Iwhich the circuit operates in this particular case, the pulses arriving at the respective output terminals 1.4 and 37 separated in time by an amount equal to (fri-D3) (fri-D1) the circuit thereby having separated the two pulses only by the additional amount of (D1-D3).

To give an illustrative example of circuit operation involving the instant invention, some actual time parameters that may advantageously -be employed will now be indicated. These values are intended to -be merely suggestive and should in no way be taken as limitations to the invention. With the time delays D1, D2 and D3 provided by delay units 13, l5 and 17 being respectively 25, 47 and 3 microseconds, the time Ta during which the level output of gate generator 1l is at its O voltage or quasistable state may be 50 microseconds. Thus, should a pulse arrive at input terminal 2o more than 50 microseconds after one has arrived at input terminal l0, the pulse at terminal lo will be delayed by the 25 microseconds provided by delay unit l, While the input pulse at 4terminal Ztl will be delayed only by the 3 microsecond delay provided by delay unit 17.

More specifically, assume that a pulse arrives at input terminal 2o sixty microseconds after the arrival of a pulse at input terminal lill. That is, with reference to FIG. 2, 13:0 and t2=60 microseconds. The pulse at terminal l@ will be delayed -by 25 microseconds, arriving at the utilization circuit 33 on lead lll at time trl-D1: (0-1-25) microseconds=25 microseconds. As described supra, the pulse at terminal 2o will be delayed by the D3 delay provided by delay unit l'', thereby arriving at the utilization circuit 3S on lead 37 at time t2-}-D3=(60+3) microseconds=63 microseconds. The output pulses are .thus separated yby (63-25)=38 to exceed au assumed minimum resolution time of 22 microseconds for the utilization circuit 38. l

Case Il: Input Pulse Arrives on Terminal 20 Before Ta A situation which is generally analogous to Case I, described supra, is the one in which a pulse arrives on terminal 2o during the time Tb but prior to time Ta. This situation is diagrammed in FIG, 3, wherein a pulse is shown arriving on terminal Ztl at time t2 with a subsequent pulse following iat time t1 on input terminal lil; the latter thereby initiates the gate generator output signal, the quasi-stable state of Which lasts for time T, as previously described.

'I'he delay units l5 and 17 are initially energized at microseconds, suflicient 'i' time t2 by the presence of the input pulse on terminal 2t?. Thus, as shown in FIG. 3, a similar output pulse will be displayed on conductor le at time ffl-.D2 and on conductor i3 at time E24-D3.

When the negative-going input pulse on terminal 2t) is delivered to AND gate 19 via lead 22, the signal on the other input lead (21) to AND gate 19 is at the upper or 4.5 volt level; AND gate i9 will therefore not be enabled. The arrival ot the input pulse on terminal 2%, when it is delivered to AND gate 21S on lead 27, however, will be effective to enable AND gate 25 due to the inversion accomplished by ineverter 24 of the gate generator output signal shown at conductor 12 in FiG. l. The two inputs to AND `gate 25 will thus both be at the lower or 0 volt level at time z2, thereby resulting in the delivery of a pulse signal to the reset terminal R of .the dip-flop 29 on lead 23. lf it is assumed, as it has been so far, that ip-op 29 is already in the reset condition, no change will occur on its output conductors 3ft and 31, which will remain respectively at their volt and 4.5 volt levels.

=From this analysis, and from a corresponding inspection of FIG. 3, it can be seen that at no time will 'both the inputs (leads lr6 and 31) to AND gate 32 be at the simultaneous lower levels necessary for enabling the gate. However, it will similarly be noted that the input leads 3G and 18 to AND gate 34 will display simultaneous lower level inputs at time 124-233, thereby enabiing AND gate 34 tand delivering a pulse signal on lead 35 through OR gate 35 and to utilization circuit 38 over conductor 37 at time The other input pulse on terminal l0 arrives thereon at time t1, shown in FIG. 3 to occur subsequent to t2. Delay unit 13 is then activated and a pulse output is straighttorwardly transmitted to the utilization circuit 3S on lead 14 at time tl-i-Dl. Since the input pulse on terminal 2% arrives thereon prior to the triggering of the gate generator il by the pulse on terminal l@ at t1, the aforementioned gate generator output plays no substantial role in this particular case. With regard to the bottom two lines of FlG. 3, it can be seen that the pulses, when de- -livered to the utilization circuit 38, are separated in time `by an amount equivalent to the dierence (trl-D1)- (fad-D9 'In terms of actual time values, it may initially be assumed that the pulse to input terminal 2d arrives thereon microseconds prior to the arrival of an input pulse on terminal 19; i.e., t2=0 and t1=20. As discussed supra in this case, the input pulse on terminal 20 will be transmitted to the utilization circuit 33 over lead 37 at time t2-}-D3=(0+3) microseconds=3 microseconds. Furthermore, the input pulse on terminal llt) will be delivered to the utilization `circuit 3S over lead i4 at time tf1-D1: (ZO-i-ZS) microseconds--45 microseconds. Thus, it can be seen that under these circumstances, pulses are delivered to the utilization circuit 38 separated in time by (45 3) microseconds=42 microseconds, suiiicient to allow the utilization circuit 35 to properly respond to each of the pulses.

Case III: Input Pulse Arrives on Terminal 20 During Ta It a pulse arrives at input terminal 2t? `during the time T, when the output signal from gate generator lll on conductor l2 in FlG. l is in its 0 -volt or quasi-stable state, as shown in the first three lines of FIG. 4, the instant invention operates to insure that at least a minimum time separation will exist .between the output pulses at terminals 14 and 37. The operation of the AND gates 19' and under these circumstances is generally similar to that described supra. Since the 0 volt pulse arrives at terminal 2i) and thus also on lead 22 during the time that the O volt level is present on conductor l2 and thus also on conductor 21, AND gate 19 will be enabled, thereby providing a negative-going pulse signal on lead 23 to the set terminal S of the flip-flop 2i'. Due to the inversion of the :output signal of gate generator ll achieved -by inverter 24, a 4.5 volt level ispresent on conductor 26 when the O volt pulse from terminal 2t? is present on lead 27; AND gate 25 will therefore not deliver any pulse input to the reset terminal R of flip-flop 29.

The ilip-ilop Z9 responds .to the input signal at its set terminal S by switching the 0 volt level at its l output terminal on lead 3i) to 4.5 rvolts and also, since the ipilops outputs continuously act as the complements of each other, by switching the prior 4,5 volt level at its 0 output on lead 3i to 0 volt, shown on the lines numbered 3i) and 3i in FIG. 4.

Since the pulse input at terminal 210 was effective to energize the delay units l5 and 17, a 0 volt Pulse will appear on leads i6 and 18 at times t2-l-D2 and t2-l-D3 respectively, as shown on the appropriately numbered lines of Fil-G. J. rTherefore, at time ffl-D2, the two inputs to AND gate 32 will both be at a 0 volt level, thereby enabling gate 3?. and providing a pulse output on lead 33. Gate 34, ion the other hand, will not be enabled, since at no time do the two input terminals (leads 13 and 31) to that gate exhibit simultaneous lower voitage levels. The pulse output from lead 33` will enengize Oi?. gate 36 and be delivered on conductor 37 to the utilization circuit 3S at time tZ-l-,Dg shown in the bottom line of FIG. 4. Since the prior arrival of a pulse on terminal l@ `oi THG. l has activated delay unit if), a pulse output will similarly be delivered at time trl-D1 to the utilization circuit 33 on conductor id as shown in the next to the bottom line of FIG. 3.

The llip-op 29 has thereby responded to the signal on its set input terminal S by blocking the passage of the pulse to input terminal 2t? through the transmission path including delay unit 17 and AND gate 34;, and has instead enabled AND gate 312` to allow the passage of the pulse at terminal 2li through the path including the delay unit l5, conductor 16, AND gate 32, lead 33, OR gate 36, and conductor 3-7 to utilization circuit 3S. The pulses thereby anrive at the utilization circuit 3S of FIG. l separated in time by an interval equivalent to the difference between (tz-l-DZ) and (Irl-D1). The additional separation introduced by the instant pulse resolu-tion circuit is that represented by ithe difference (D2-D1). lThe utilization circuit 3S is thereby assured of having suicient time separation between the input signals on leads 14 and 37 to operate properly regardless of how proximately within the period Ta the pulses at input terminals i0 and 20 arrive.

A specic illustration of Case lI=I operation of this invention would be where a pulse arrives at input terminal 29 only l5 microseconds after one has priorly arrived at input terminal it? (see FIG. 4). With t1=0 and t2=l5 microseconds, the delay unit 13 is energized to delay the pulse on lead 1d by 25 microseconds and to thus deliver a pulse output to utilization circuit 33 on lead 14 at time r1-}-D1=(0}25) microseconds=25 microseconds. By the action `described supra for Case lll, the pulse at terminal 2d will be delayed by the time delay provided by delay unit l5, a pulse output thus a pearing on output lead 37 at time t2-}-D2=(i5}47) microseconds=62 microseconds. The pulses delivered to the utilization circuit 38 are therefore (62-25) mioroseconds=37 microseconds apart; this is sufciently greater than the 22 microsecond minimum resolution time assumed to be required by the utilization circuit 38', whereas absent the instant invention, the l5 microsecond separation at input terminals ll and Ztl would not have allowed the utilization circuit 3S to properly respond to both signals.

Cases IV: When Pulsar Arrive at Terminals 10 and 20 Simultaneously The situation with which a pulse resolution circuit must be able to deal especially effectively is the one in which pulses arrived simultaneously at the circuts inputs. With regard to the instant invention and particularly FlGS. l and 5 thereof, the specific instance with which we are now concerned is where a pulse arrives at input terminal 10 at time t1 at the same time that a pulse arrives at terminal 2t? at time r2; that is, when t1 equals t2.

As is the case when any pulse arrives at terminal l of FIG. 1, the generator 11 is activated to produce its gating output signal on conductor 12, said signal being transmitted to conductor "2i, and after inversion by inverter 24, to conductor 26. The signals which initially appear at terminals 21 and 26 when pulses arrived at input terminals and 26 simultaneously are transient signals and as such may be neither the 4.5 volt level nor the O volt level to which levels the circuit is normally operative to respond.

Thus, there exists the initial possibility that during the transients denoted as r1 and T2 in the pulse sketch shown at conductor 12 of FIG. l, both AND gates 19 and 25 may be enabled simultaneously, A-ND gate 19 by the negative-going transient during f2 yfor example and the lower level voltage pulse from terminal 2); and AND gate 2S by the inverted transient on conductor 2d and the lower level voltage pulse from terminal 2i) on conductor 27. This would result in simultaneous pulsing of both the set and reset terminals, S and R respectively, of the flip-flop 219, on conductors 23 and 218 respectively. However, as is well known, a bistable device such as flip-flop 29 does not respond to two such inputs and instead dis criminates between the two, as a result of minute component differences within the dip-dop, to select one yof the two signals. As will now be demonstrated, the instant invention is arranged so as to provide the predetermined minimum resolution time between the pulses independently fof the input signal selected by the Hip-flop 29.

It is initially assumed that the input signal from conduetor 23 to the set terminal S of ythe flip-flop 2;? controls the ip-op in the case of simultaneous pulsing; this is the situation indicated in the time diagram or" FIG. 5. Thus, when the iiiplops input terminals are pulsed, the l output on `lead '36 switches from its normal i) vo-l-t level to the 4.5 volt level while the 0' output on lead 31 icomplementarily switches from the 4.5 volt level to the 0` volt level. As with the above-described operational situations with regard to the pulses arriving at input terminals lt) and 2Q, the input pulse at terminal Ztl at time t2 initially activates delay units 15 and 17 respectively,l producing a pulse output on lead i6 at time ITI-D2 and a similar out-put on lead 18 at the earlier time trl-D3. Regarding the two pairs of inputs to output AND gates 3?. and 34 as :shown in FIG. 5, at time rZ-,l-Dg both inputs to gate 32 are at the 0 volt level, while at no time are both inputs to gate 34 simultaneously at such a le el. Therefore, AND gate 32 will be enabled to allow passage of the pulse output on conductor 3G to OR gate 35 and consequently to lead 37 and utilization circuit 3S at time ZTI-D2; no pulse signal will, however, be delivered on lead 135. Since the pulse input terminal 10 had plriorly energized delay unit l, an output pulse signal will appear on conductor 14 at time t1-|D1. From the bottom two lines of FIG. 5, it can be seen that the pulses on conductors 14 and 37 are transmitted to the utilization circuit separated by (l2-|-D2)-(tll-D1). Furthermore, since in the case of simultaneous arrival of pulses at terminals l@ and 24?, t2=r1, the pulse resolution circuit has provided an amount of delay equivalent to the difference D2-D1.

Again using the time values referred to hereinabove, this situation is one in which, as shown in FIG. 5, t1=t2, and in which delay unit 13 will be energized to provide a pulse output signal on lead 14 to utilization circuit 38 at ytime t1-l-D1=(0,+25) microseconds=25 microseconds. Under the present assumption, delay unit will be effective to delay the input pulse at terminal 20, providing a pulse output to utilization circuit 38 on lead 37 at time t2-{-D2=(O|47) microseconds=47 microseconds. The instant circuit has thus furnished the utilization circuit 38 with pulses now separated in time by (47-25) 10 microseconds=22 microseconds, the established minimum resolution time needed by utilization circuit 38.

Due to the transient condition of the output signal of -gate generator 11 mentioned above, a second possible situation with regard to the iiipdiop 29 could be that the input pulse on lead 28 to the reset terminal R of the iiip-liop 29 would control that devices operation. If such were to be the case, the lip-iiops operation would be identical with that shown on the lines numbered 30 and 31 of FIG. 2; that is, the l output on lead 30 would remain at its stable 0 volt level, assumed previously while the 0 output on lead 31 would similarly remain at its 4.5 Volt level.

With the activation of delay units and 17 by the input pulse at terminal Ztl, pulse output signals would again be produced on lead 16 at time tg-l-Dg and on lead i8 at time M24-D3. Under the circumstances assumed for -this particular case, however, the simultaneous lower level voltages would appear on the two inputs to AND ygate 34 at time ITI-D3, rather than on the inputs to AND gate 32, the latter gate thus being disabled in this situation. With AND gate 34 thereby enabled, a pulse signal will be transmitted on conductor 35 through OR gate 36 and on conductor 37 to the utilization circuit 3d at time tz-l-Dg. The pulse output due to the input 0 volt pulse on terminal 10 Will be transmitted through delay unit 13, appearing on lead 14 connected to utilization circuit 3S at time ttyl-D1. The separation between the output pulses on leads 114 and 37 in such a case would be an interval represented by the diiierence (t1+D1)(2"-{D3); with t1 being equal to t2 in the case of simultaneous arrival of pulses at terminals l@ and 2%, the actual delay interposed by the circuit is that represented by the difference D1-D3.

ln specific time terms, 13:13, and an output pulse will again appear on lead 14 at time t1-l-D1=(0j+25) microseconds=25 microseconds, due to the energization of delay unit i3. With the input pulse at terminal 20' assumed now to be eiiectively delayed by the delay unit 17, there will be a pulse output on lead 37 at time t2f+D3=(G-{-3) microseconds=3 microseconds. The resultant delay between the pulses thereby provided to utilization circuit 33 on leads lll and 37 is (Z5-3) microseconds=22 microseconds, this again being the minimum allowable resolution time for utilization circuit 3S.

It is recalled that if the input signal on lead 23 to the set terminal S of iiip-iiop 29 controlled the `iiip-fflops operation as in our initial assumption supra, the time separation provided by the circuit was D2-Db while in the situation described immediately above, wherein the signal trom lead 23 to the reset input R of flip-hop 2g was assumed to have cont-rolled the operation of the flip-dop, the delay was D1-D3. A third possible situation in the case of simultaneous input pulses with regard to ip-ilop 29 is that the ip-ilop does not receive a pulse on the set input 23 and also does not receive a pulse on the reset input 23. -In this case, the lijp-iop remains in its previous state andthe appropriate one of the two above-mentioned examples will apply, with an output pulse separation of DZ-Dl or D1-D3 being provided.

The independence of operation of this circuit from the uncertainty associate-d with the iiip-iiops outputs in the case of simultaneous pulsing of its input terminals is eiectively provided by equating those two time differentials. In representative terms (D2-D1) is made equal to (D1-D3), and it has been shown supra that each of these differentials may be illustratively equal to 22 microseconds. It is thus seen that the circuit will properly operate to suliiciently resolve simultaneously arriving pulses at terminals l0 and 2@ when they aredelivered to the utilization circuit on conductors `14 and 37 respectively, by a minimum predetermined amount which is independent of the possible uncertain operation of the flip-dop 29 and the gates 19 and 25.

The maximum amount of separation of output pulses is provided by the circuit during Case vIll operation, when :a pulse arrives at input terminal 26 just at the end of the illustrative microsecond interval following an input -pulse to terminal 1G; if AND gate 32 is thereby enabled, the time differential between the output pulses on leads 37 and 14 will be that represented by the difference [(50447) 25] microseconds=72 microseconds. Under no circumstances, however, can pulses arriving at terminals l@ and 2d be separated, when they are eventually delivered to the utilization circuit S8, by less than the predetermined minimum interval which in the Specific examples cited has been given as 22 microseconds.

It is understood that the above-described arrangements are merely illustrative of the principles of this invention. Numerous and varied other arrangements can readily be devised in accordance with these principles by those skilled in the art, Without departing from the spirit and scope of the invention.

What is claimed is:

l. In combination for providing at least a predetermined cresolution period between randomly occurring pulses, a utilization circuit, a irst input terminal and a second input terminal, a plurality of delay elements of different time values, a first of said -delay elements connected between said first input terminal and said utilization circuit, gate generator means for providing an output signal of predetermined interval, bistable switching means, first gating means coupling said generator means to said bistable switching means and responsive to similarly polarized signals from said -gate generator and from said second input terminal, second gating means responsive to similarly polarized signals from said bistable switching means and from a second and a third of said delay elements, :and means including said bistable switching means for selectively determining which one of said second and said third delay elements will effectively delay said pulses arriving at said second input terminal.

2. A circuit in accordance with claim l including in addition output gating means, and wherein said pulses are of two electrical levels, and means including said first gating means and said second gating means responsive to the simultaneous application of a lower of said levels to control said bistable switching means and said output gating means.

3. A circuit in accordance with claim 2 including means for disabling said second gating means if said pulses arrive at said first and said second input terminals during said predetermined interval.

4. A pulse resolution circuit compirsing first and second input terminals, a first transmission path including first delay means coupled to said rst input terminal, second and third transmission paths respectively including second and third delay means coupled to said second input terminal, gate generator means responsive to signals at said first input terminal to produce an output signal of predetermined interval, control means operative to selectively block the passage of signals from said second input terminal through one of said second and said third transmission paths, first gating means responsive to said gate generator output signal and to said signals at said second input terminal to deliver a signal to said control means, and means including said control means for selectively delaying the passage of said signals from said second input terminal by the time delay of said second delay means if said signals arrive at said second input terminals within said predetermined interval of the arrival of said signals at said first input terminal and by the time delay of said third delay means if said signals arrive at said second input terminal without said predetermined interval of the arrival of said signals at said first input terminal.

5. A pulse resolution circuit in accordance with claim 4 wherein said control means includes a flip-dop device.

6. A pulse resolution circuit in accordance with claim 5 further comprising second gating means responsive to the simultaneous application of similarly polarized signals from said second and said third delay means and from said flip-hop to selectively pass said signals from said second input terminal through one of said second and said third paths.

7. A pulse resolution circuit in accordance with claim 5 including in addition inverter means, wherein said first gating means includes a first AND gate responsive to said gate generator output signal and to signals at said second input terminal Within said predetermined interval to deliver a signal to one input of said Hip-flop, and a second AND gate responsive to inverted signals through said inverter means from said gate generator means and to signals at said second input terminal without said predetermined interval to deliver a signal to the other input of said flip-flop.

8. A pulse resolution circuit for providing at least a predetermined time separation between randomly occurring first and second signals comprising means for applying said first signal to a first path having a first predetermined delay interval, means for directly applying said second signal both to a second path and to a third path, said second path having a delay appreciably greater than and said third path having a delay appreciably less than that of said first path, first control means responsive to the application of said first signal to said first path and to the application of said second signal to said second and third paths for maintaining said third path blocked and for simultaneously unblocking said second path both during the passage of said first signal through said first path for said first delay interval and for an equal interval thereafter, and second control means responsive to said application of said first signal and to said application of said second signal for maintaining said second path blocked and for simultaneously unblocking said third path after the expiration of said equal interval.

9. A pulse resolution circuit for providing at a utilization circuit a delay of at least a predetermined time separation between pulses randomly applied to a plurality of distinct input terminals comprising generator means responsive to the arrival of a first one of said pulses at one of said terminals for furnishing a gating signal of a predetermined interval, a plurality of distinct delay means connected between said input terminals and said utilization circuit, controlling means jointly responsive to said gating signal and to one of said randomly applied pulses at another of said input terminals for selectively determining which one of said plurality of delay means will delay saidl last-mentioned one of said pulses, said controlling means including a first AND gate energized by said gating signal during said predetermined interval, a second AND gate blocked during said predetermined interval, and bistable switching means selectively responsive to signals from said first and said second AND gate, output gating means connected to said bistable switching means and to said plurality of delay means for selectively blocking the passage of pulses through said plurality of delay means, said output gating means including a third and a fourth AND gate controlled by said bistable switching means, said third AND gate blocking pulses from being transmitted through one of said plurality of delay means if said one of said pulses applied at said another of said input terminals switches said bistable switching means within said predetermined interval of the arrival of said first one of said pulses at said firstmentioued one of said input terminals and said fourth AND gate blocking said pulses from being transmitted through a second of said plurality of delay means if said one of said pulses applied at said another of said input terminals switches said bistable switching means without said predetermined interval.

10. A pulse resolution circuit comprising a utilization circuit, generator means for providing a stable voltage level output and a quasi-stable voltage level output, bistable switching means, a plurality of delay elements, first gating means responsive to a transition between said stable and said quasi-stable levels to deliver signals to said bistable switching means, and second gating means coupled to said bistable switching means and to a iirst and a second of said plurality of delay elements, said second gating means being selectively responsive to signals from said bistable switching means and from said first and said second of said plurality of delay elements to provide a signal to said utilization circuit.

11. A pulse resolution circuit in accordance with claim 10 wherein said generator means provides said quasistable level for a predetermined interval exclusive of the duration of said transition between said stable and said quasi-stable levels and further comprising input means for energizing said first gating means during said duration 15 2,858,429

of said transition.

12. A pulse resolution circuit in accordance with claim 1l wherein said first gating means includes a first and a second AND gating means jointly energizable by signals from said input means during said duration of said transition, said first AND gating means being individually energized by signals from said input means Within said predetermined interval, and said AND gating means being individually energized by signals from said input means without said predetermined interval and without said 10 duration of said transition.

References Cited in the iile of this patent UNITED STATES PATENTS Heywood Oct. 28, 1958 3,019,350 Gauthey Jan. 30, 1962 

8. A PULSE RESOLUTION CIRCUIT FOR PROVIDING AT LEAST A PREDETERMINED TIME SEPARATION BETWEEN RANDOMLY OCCURRING FIRST AND SECOND SIGNALS COMPRISING MEANS FOR APPLYING SAID FIRST SIGNAL TO A FIRST PATH HAVING A FIRST PREDETERMINED DELAY INTERVAL, MEANS FOR DIRECTLY APPLYING SAID SECOND SIGNAL BOTH TO A SECOND PATH AND TO A THIRD PATH, SAID SECOND PATH HAVING A DELAY APPRECIABLY GREATER THAN AND SAID THIRD PATH HAVING A DELAY APPRECIABLY LESS THAN THAT OF SAID FIRST PATH, FIRST CONTROL MEANS RESPONSIVE TO THE APPLICATION OF SAID FIRST SIGNAL TO SAID FIRST PATH AND TO THE APPLICATION OF SAID SECOND SIGNAL TO SAID SECOND AND THIRD PATHS FOR MAINTAINING SAID THIRD PATH BLOCKED AND FOR SIMULTANEOUSLY UNBLOCKING SAID SECOND PATH BOTH DURING THE PASSAGE OF SAID FIRST SIGNAL THROUGH SAID FIRST PATH FOR SAID FIRST DELAY INTERVAL AND FOR AN EQUAL INTERVAL THEREAFTER, AND SECOND CONTROL MEANS RESPONSIVE TO SAID APPLICATION OF SAID FIRST SIGNAL AND TO SAID APPLICATION OF SAID SECOND SIGNAL FOR MAINTAINING SAID SECOND PATH BLOCKED AND FOR SIMULTANEOUSLY UNBLOCKING SAID THIRD PATH AFTER THE EXPIRATION OF SAID EQUAL INTERVAL. 